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rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad7703 lc 2 mos 20-bit a/d converter features monolithic 16-bit adc 0.0015% linearity error on-chip self-calibration circuitry programmable low-pass filter 0.1 hz to 10 hz corner frequency 0 v to +2.5 v or 2.5 v analog input range 4 ksps output data rate flexible serial interface ultralow power applications industrial process control weigh scales portable instrumentation remote data acquisition functional block diagram 4 17 9 10 8 5 19 20 13 dgnd av dd dv dd av ss dv ss sc1 sc2 14 15 7 6 a gnd a in v ref calibration sram calibration microcontroller cal bp/ up sleep clock generator sdata sclk 2 18 clkin clkout mode cs drdy ad7703 analog modulator 12 11 6-pole gaussian low-pass digital filter 20-bit charge balance a/d converter 3 16 1 serial interface logic general description the ad7703 is a 20-bit adc that uses a s - d conversion tech- nique. the analog input is continuously sampled by an analog modulator whose mean output duty cycle is proportional to the input signal. the modulator output is processed by an on-chip digital filter with a six-pole gaussian response, which updates the output data register with 16-bit binary words at word rates up to 4k hz. the sampling rate, filter corner frequency, and output word rate are set by a master clock input that may be supplied externally, or by a crystal controlled on-chip clock oscillator. the inherent linearity of the adc is excellent and endpoint accu- racy is ensured by self-calibration of zero and full scale, which may be initiated at any time. the self-calibration scheme can also be extended to null system offset and gain errors in the input channel. the output data is accessed through a flexible serial port, which has an asynchronous mode compatible with uarts and two synchronous modes suitable for interfacing to shift registers or the serial ports of industry-standard microcontrollers. cmos construction ensures low power dissipation, and a power- down mode reduces the idle power consumption to only 10 w. product highlights 1. the ad7703 offers 20-bit resolution coupled with outstanding 0.0003% accuracy. 2. no missing codes ensures true, usable, 20-bit dynamic range, removing the need for programmable gain and level-setting circuitry. 3. the effects of temperature drift are eliminated by on-chip self-calibration, which removes zero and gain error. external circuits can also be included in the calibration loop to remove system offsets and gain errors. 4. flexible synchronous/asynchronous interface allows the ad7703 to interface directly to the serial ports of industry- standard microcontrollers and dsp processors. 5. low operating power consumption and an ultralow power standby mode make the ad7703 ideal for loop-powered remote sensing applications, or battery-powered portable instruments.
rev. e ? ad7703?pecifications parameter a/s version 2 b version 2 c version 2 unit test conditions/comments static performance resolution 20 20 20 bits integral nonlinearity, t min to t max 0.0015 0.0007 0.0003 % fsr typ 25 c 0.003 0.0015 0.0008 % fsr max t min to t max 0.003 0.0015 0.0012 % fsr max differential nonlinearity, t min to t max 0.5 0.5 0.5 lsb typ guaranteed no missing codes positive full-scale error 3 4 4 4 lsb typ 16 16 16 lsb max full-scale drift 4 19/37 19 19 lsb typ unipolar offset error 3 4 4 4 lsb typ 16 16 16 lsb max unipolar offset drift 4 26 26 26 lsb typ temp range: 0 c to +70 c 67 +48/ C 400 67 67 lsb typ specified temp range bipolar zero error 3 4 4 4 lsb typ 16 16 16 lsb max bipolar zero drift 4 13 13 13 lsb typ temp range: 0 c to +70 c 34 +24/ C 200 34 34 lsb typ specified temp range bipolar negative full-scale errors 3 8 8 8 lsb typ 32 32 32 lsb max bipolar negative full-scale drift 4 10/20 10 10 lsb typ noise (referred to output) 1.6 1.6 1.6 lsb rms typ dynamic performance sampling frequency, f s f clkin /256 f clkin /256 f clkin /256 hz output update rate, f out f clkin /1024 f clkin /1024 f clkin /1024 hz filter corner frequency, f C 3 db f clkin /409,600 f clkin /409,600 f clkin /409,600 hz settling time to 0.0007% fs 507904/f clkin 507904/f clkin 507904/f clkin sec for full-scale input step system calibration positive full-scale calibration range v ref + 0.1 v ref + 0.1 v ref + 0.1 v max system calibration applies to positive full-scale overrange v ref + 0.1 v ref + 0.1 v ref + 0.1 v max unipolar and bipolar ranges. negative full-scale overrange C (v ref + 0.1) C (v ref + 0.1) C (v ref + 0.1) v max after calibration, if a in > v ref , maximum offset calibration ranges 5, 6 the device will output all 1s. unipolar input range C (v ref + 0.1) C (v ref + 0.1) C (v ref + 0.1) v max if a in < 0 (unipolar) or C v ref bipolar input range C 0.4 v ref to +0.4 v ref C 0.4 v ref to +0.4 v ref C 0.4 v ref to +0.4 v ref v max (bipolar), the device will input span 7 0.8 v ref 0.8 v ref 0.8 v ref v min output all 0s. 2 v ref + 0.2 2 v ref + 0.2 2 v ref + 0.2 v max analog input unipolar input range 0 to 2.5 0 to 2.5 0 to 2.5 v bipolar input range 2.5 2.5 2.5 v input capacitance 20 20 20 pf typ input bias current 1 111na typ logic inputs all inputs except clkin v inl , input low voltage 0.8 0.8 0.8 v max v inh , input high voltage 2.0 2.0 2.0 v min clkin v inl , input low voltage 0.8 0.8 0.8 v max v inh , input high voltage 3.5 3.5 3.5 v min i in , input current 10 10 10 a max logic outputs v ol , output low voltage 0.4 0.4 0.4 v max i sink = 1.6 ma v oh , output high voltage dv dd C 1dv dd C 1dv dd C 1v min i source = 100 a floating state leakage current 10 10 10 a max floating state output capacitance 999pf typ power requirements power supply voltages analog positive supply (av dd ) 4.5/5.5 4.5/5.5 4.5/5.5 v min/v max for specified performance digital positive supply (dv dd ) 4.5/av dd 4.5/av dd 4.5/av dd v min/v max analog negative supply (av ss ) C 4.5/ C 5.5 C 4.5/ C 5.5 C 4.5/ C 5.5 v min/v max digital negative supply (dv ss ) C 4.5/ C 5.5 C 4.5/ C 5.5 C 4.5/ C 5.5 v min/v max calibration memory retention power supply voltage 2.0 2.0 2.0 v min (t a = 25 c; av dd = dv dd = +5 v; av ss = dv ss = ? v; v ref = +2.5 v; f clkin = 4.096 mhz; bp/ up = +5 v; mode = +5 v; a in source resistance = 1 k 1 with 1 nf to agnd at a in ; unless otherwise noted.)
rev. e ad7703 ? parameter a/s version 2 b version 2 c version 2 unit test conditions/comments power requirements dc power supply currents 8 analog positive supply (ai dd ) 2.7 2.7 2.7 ma max typically 2 ma digital positive supply (di dd )2 22 ma max typically 1 ma analog negative supply (ai ss ) 2.7 2.7 2.7 ma max typically 2 ma digital negative supply (di ss ) 0.1 0.1 0.1 ma max typically 0.03 ma power supply rejection 9 positive supplies 70 70 70 db typ negative supplies 75 75 75 db typ power dissipation normal operation 37 37 37 mw max sleep = logic 1, typically 25 mw standby operations 10 sleep = logic 0, a, b, c 20 20 20 w max typically 10 w s404040 w max notes 1 the a in pin presents a very high impedance dynamic load that varies with clock frequency. a ceramic 1 nf capacitor from the a in pin to agnd is necessary. source resistance should be 750 or less. 2 temperature ranges are as follows: a, b, c versions: ?0 c to +85 c; s version: ?5 c to +125 c. 3 applies after calibration at the temperature of interest. full-scale error applies for both unipolar and bipolar input ranges. 4 total drift over the specified temperature range after calibration at power-up at 25 c. this is guaranteed by design and/or characterization. recalibration at any temperature will remove these errors. 5 in unipolar mode, the offset can have a negative value (? ref ) such that the unipolar mode can mimic bipolar mode operation. 6 the specifications for input overrange and for input span apply additional constraints on the offset calibration range. 7 for unipolar mode, input span is the difference between full scale and zero scale. for bipolar mode, input span is the differen ce between positive and negative full-scale points. when using less than the maximum input span, the span range may be placed anywhere within the range of (v ref + 0.1). 8 all digital outputs unloaded. all digital inputs at 5 v cmos levels. 9 applies in 0.1 hz to 10 hz bandwidth. psrr at 60 hz will exceed 120 db due to the digital filter. 10 clkin is stopped. all digital inputs are grounded. specifications subject to change without notice. absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) dv dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +6 v dv dd to av dd . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v dv ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ? v av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +6 v av ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ? v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v digital input voltage to dgnd . . . . ?.3 v to dv dd + 0.3 v analog input voltage to agnd . . . av ss ?0.3 v to av dd + 0.3 v input current to any pin except supplies 2 . . . . . . . . 10 ma operating temperature range industrial (a, b, c versions) . . . . . . . . . . . ?0 c to +85 c extended (s version) . . . . . . . . . . . . . . . . ?5 c to +125 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . . 300 c power dissipation (dip package) to 75 c . . . . . . . . . 450 mw derates above 75 c by . . . . . . . . . . . . . . . . . . . . . 10 mw/ c power dissipation (soic package) to 75 c . . . . . . . 250 mw derates above 75 c by . . . . . . . . . . . . . . . . . . . . . . 15 mw/ c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. ordering guide linearity temperature error package model range (% fsr) options * ad7703an ?0 c to +85 c 0.003 n-20 ad7703bn ?0 c to +85 c 0.0015 n-20 ad7703cn ?0 c to +85 c 0.0012 n-20 ad7703ar ?0 c to +85 c 0.003 r-20 ad7703br ?0 c to +85 c 0.0015 r-20 ad7703cr ?0 c to +85 c 0.0012 r-20 ad7703aq ?0 c to +85 c 0.003 q-20 ad7703bq ?0 c to +85 c 0.0015 q-20 ad7703cq ?0 c to +85 c 0.0012 q-20 ad7703sq ?5 c to +125 c 0.003 q-20 * n = plastic dip; r = soic; q = cerdip. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7703 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. e ? ad7703 limit at t min , t max limit at t min , t max parameter (a, b versions) (s, t versions) unit conditions/comments f clkin 3, 4 200 200 khz min master clock frequency: internal gate oscillator 55 mhz max typically 4.096 mhz 200 200 khz min master clock frequency: externally supplied 55 mhz max t r 5 50 50 ns max digital output rise time. typically 20 ns. t f 5 50 50 ns max digital output fall time. typically 20 ns. t 1 00 ns min sc1, sc2 to cal high setup time t 2 50 50 ns min sc1, sc2 hold time after cal goes high t 3 6 1000 1000 ns min sleep high to clkin high setup time ssc mode t 4 7 3/f clkin 3/f clkin ns max data access time (cs low to data valid) t 5 100 100 ns max sclk falling edge to data valid delay (25 ns typ) t 6 250 250 ns min msb data setup time. typically 380 ns. 7 300 300 ns max sclk high pulsewidth. typically 240 ns. t 8 790 790 ns max sclk low pulsewidth. typically 730 ns. t 9 8 l/f clkin + 200 l/f clkin + 200 ns max sclk rising edge to hi-z delay (l/f clkin + 100 ns typ) t 10 8, 9 4/f clkin + 200 4/f clkin + 200 ns max cs high to hi-z delay sec mode f sclk 55 mhz max serial clock input frequency t 11 35 35 ns min sclk input high pulsewidth t 12 160 160 ns min sclk low pulsewidth t 13 7, 10 160 160 ns ma x data access time (cs low to data valid). typically 80 ns. t 14 11 150 150 ns max sclk falling edge to data valid delay. typically 75 ns. t 15 8 250 250 ns max cs high to hi-z delay t 16 8 200 200 ns max sclk falling edge to hi-z delay. typically 100 ns. notes 1 sample tested at 25 c to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 see figures 1 to 6. 3 clkin duty cycle range is 20% to 80%. clkin must be supplied whenever the ad7703 is not in sleep mode. if no clock is present i n this case, the device can draw higher current than specified and possibly become uncalibrated. 4 the ad7703 is production tested with f clkin at 4.096 mhz. it is guaranteed by characterization to operate at 200 khz. 5 specified using 10% and 90% points on waveform of interest. 6 in order to synchronize several ad7703s together using the sleep pin, this specification must be met. 7 t 4 and t 13 are measured with the load circuit of figure 1 and defined as the time required for an output to cross 0.8 v or 2.4 v. 8 t 9 , t 10 , t 15 , and t 16 are derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the mea sured number is then extrapolated back to remove the effects of charging or discharging the 100 pf capacitor. this means that the time quote d in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitance. 9 if cs is returned high before all 20 bits are output, the sdata and sclk outputs will complete the current data bit and then go to high impedance. 10 if cs is activated asynchronously to drdy, cs will not be recognized if it occurs when drdy is high for four clock cycles. the propagation delay time may be as great as four clkin cycles plus 160 ns. to guarantee proper clocking of sdata when using asynchronous cs, the sclk input sho uld not be taken high sooner than four clkin cycles plus 160 ns after cs goes low. 11 sdata is clocked out on the falling edge of the sclk input. specifications subject to change without notice. timing characteristics 1, 2 (av dd = dv dd = +5 v 10%; av ss = dv ss = ? v 10%; agnd = dgnd = o v; f clkin = 4.096 mhz; input levels: logic o = o v, logic 1 = dv dd ; unless otherwise noted.) c l 100pf to output pin i oh 200 a 2.1v + i ol 1.6ma figure 1. load circuit for access time and bus relinquish time cal sc1, sc2 sc1, sc2 valid t 1 t 2 figure 2. calibration control timing clkin sleep t 3 figure 3. sleep mode timing
rev. e ad7703 ? data va l i d t 15 hi-z sdata cs figure 5b. sec mode data hold time hi-z db19 db18 db1 db0 hi-z sclk sdata clkin cs hi-z t 7 t 8 t 5 t 9 t 4 t 8 hi-z figure 6. ssc mode timing diagram definition of terms linearity error this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are zero-scale (not to be confused with bipolar zero), a point 0.5 lsb below the first code transition (000 . . . 000 to 000 . . . 001) and full-scale, a point 1.5 lsb above the last code transition (111 . . . 110 to 111 . . . 111). the error is expressed as a percentage of full scale. differential linearity error this is the difference between any code? actual width and the ideal (1 lsb) width. differential linearity error is expressed in lsb. a differential linearity specification of 1 lsb or less guarantees monotonicity. positive full-scale error positive full-scale error is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal (v ref 3/2 lsb). it applies to both positive and negative analog input ranges and is expressed in microvolts. unipolar offset error unipolar offset error is the deviation of the first code transition from the ideal (agnd + 0.5 lsb) when operating in the uni polar mode. bipolar zero error this is the deviation of the midscale transition (0111 . . . 111 to 1000 . . . 000) from the ideal (agnd ?0.5 lsb) when operating in the bipolar mode. it is expressed in microvolts. bipolar negative full-scale error this is the deviation of the first code transition from the ideal (? ref + 0.5 lsb) when operating in the bipolar mode. positive full-scale overrange positive full-scale overrange is the amount of overhead available to handle input voltages greater than +v ref (for example, noise peaks or excess voltages due to system gain errors in system calibration routines) without introducing errors due to overloading the analog modulator or overflowing the digital filter. negative full-scale overrange this is the amount of overhead available to handle voltages below ? ref without overloading the analog modulator or overflowing the digital filter. note that the analog input will accept negative voltage peaks even in the unipolar mode. offset calibration range in the system calibration modes (sc2 low), the ad7703 calibrates its offset with respect to the a in pin. the offset calibration range specification defines the range of voltages, expressed as a percentage of v ref , that the ad7703 can accept and still accurately calibrate offset. full-scale calibration range this is the range of voltages that the ad7703 can accept in the system calibration mode and still correctly calibrate full scale. input span in system calibration schemes, two voltages applied in sequence to the ad7703? analog input define the analog input range. the input span specification defines the minimum and maximum input voltages from zero to full scale that the ad7703 can accept and still accurately calibrate gain. the input span is expressed as a percentage of v ref. data va l i d t 10 hi-z sdata cs figure 4. ssc mode data hold time hi-z db18 db1 db0 hi-z sdata drdy cs t 12 t 11 t 13 t 14 sclk t 16 db19 figure 5a. sec mode timing diagram
rev. e ? ad7703 pin configuration dip, cerdip, soic mode sc1 dgnd clkout clkin a gnd dv ss av ss a in v ref sdata sclk sc2 cal av dd dv dd drdy cs bp/ up sleep top view (not to scale) ad7703 1 2 3 4 5 6 7 8 9 10 14 13 12 11 20 19 18 17 16 15 table i. bit weight table (2.5 v reference voltage) unipolar mode bipolar mode ppm ppm v lsb % fs fs lsb % fs fs 0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12 1.192 0.5 0.0000477 0.48 0.26 0.0000238 0.24 2.384 1.00 0.0000954 0.95 0.5 0.0000477 0.48 4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95 9.537 4.00 0.0003814 3.81 2.00 0.0001907 1.91 pin function descriptions pin no. mnemonic description 1 mode selects the serial interface mode. if mode is tied to dgnd, the synchronous external clocking (sec) mode is selected. sclk is configured as an input, and the output appears without formatting, the msb coming first. if mode is tied to +5 v, the ad7703 operates in the synchronous self-clocking (ssc) mode. sclk is configured as an output, with a clock frequency for f clkin /4 and 25% duty cycle. 2 clkout clock output to generate an internal master clock by connecting a crystal between clkout and clkin. if an external clock is used, clkout is not connected. 3 clkin clock input for external clock. 4, 17 sc 1, sc 2 system calibration pins. the state of these pins, when cal is taken high, determines the type of calibration performed. 5 dgnd digital ground. ground reference for all digital signals. 6dv ss digital negative supply, C 5 v nominal. 7av ss analog negative supply, C 5 v nominal. 8 agnd analog ground. ground reference for all analog signals. 9a in analog input. 10 v ref voltage reference input, 2.5 v nominal. this determines the value of positive full scale in the unipolar mode and the value of both positive and negative full scale in the bipolar mode. 11 sleep sleep mode pin. when this pin is taken low, the ad7703 goes into a low power mode with typically 10 w power consumption. 12 bp/ up bipolar/unipolar mode pin. when this pin is low, the ad7703 is configured for a unipolar input range going from agnd to v ref . when pin 12 is high, the ad7703 is configured for a bipolar input range, v ref . 13 cal calibration mode pin. when cal is taken high for more than four cycles, the ad7703 is reset and performs a calibration cycle when cal is brought low again. the cal pin can also be used as a strobe to synchronize the operation of several ad7703s. 14 av dd analog positive supply, 5 v nominal. 15 dv dd digital positive supply, 5 v nominal. 16 cs chip select input. when cs is brought low, the ad7703 will begin to transmit serial data in a format determined by the state of the mode pin. 18 drdy data ready output. drdy is low when valid data is available in the output register. it goes high after trans- mission of a word is completed. it also goes high for four clock cycles when a new data-word is being loaded into the output register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not. 19 sclk serial clock input/output. the sclk pin is configured as an input or output, dependent on the type of serial data transmission that has been selected by the mode pin. when configured as an output in the synchronous self-clocking mode, it has a frequency of f clkin /4 and a duty cycle of 25%. 20 sdata serial data output. the ad7703 s output data is available at this pin as a 20-bit serial word.
rev. e ad7703 ? general description the ad7703 is a 20-bit a/d converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those representing chemical, physical, or biological processes. it contains a charge-balancing ( - ) adc, calibration microcontroller with on-chip static ram, clock oscillator, and serial communications port. the analog input signal to the ad7703 is continuously sampled at a rate determined by the frequency of the master clock, clkin. a charge-balancing a/d converter ( - modulator) converts the sampled signal into a digital pulse train whose duty cycle contains the digital information. a six-pole gaussian digital low-pass filter processes the output of the - modulator and updates the 20-bit output register at a 4 khz rate. the output data can be read from the serial port randomly or periodically at any rate up to 4 khz. ad7703 mode sdata sc1 dgnd clkout clkin a gnd sclk sc2 cal cs bp/ up dv ss dv dd sleep range select calibrate analog input analog ground ?v analog supply 0.1 f +5v analog supply 2.5v 0.1 f 0.1 f drdy 0.1 f 10 f av dd v ref a in av ss vo ltag e reference 10 f data ready read (transmit) serial clock serial data figure 7. typical system connection diagram the ad7703 can perform self-calibration using the on-chip calibration microcontroller and sram to store calibration parameters. a calibration cycle may be initiated at any time using the cal control input. other system components may also be included in the calibra- tion loop to remove offset and gain errors in the input channel. for battery operation, the ad7703 also offers a standby mode that reduces idle power consumption to typically 10 w. theory of operation the general block diagram of a - adc is shown in figure 8. it contains the following elements: 1. a sample-hold amplifier 2. a differential amplifier or subtracter 3. an analog low-pass filter 4. a 1-bit a/d converter (comparator) 5. a 1-bit dac 6. a digital low-pass filter analog low-pass filter comparator digital data s/h amp dac digital filter figure 8. general - adc in operation, the analog signal sample is fed to the subtracter, along with the output of the 1-bit dac. the filtered difference signal is fed to the comparator, whose output samples the differ- ence signal at a frequency many times that of the analog signal sampling frequency (oversampling). oversampling is fundamental to the operation of - adcs. using the quantization noise formula for an adc snr = (6.02 number of bits + 1.76) db a 1-bit adc or comparator yields an snr of 7.78 db. the ad7703 samples the input signal at 16 khz, which spreads the quantization noise from 0 khz to 8 khz. since the specified analog input bandwidth of the ad7703 is only 0 hz to 10 hz, the noise energy in this bandwidth would be only 1/800 of the total quantization noise, even if the noise energy were spread evenly throughout the spectrum. it is reduced still further by analog filtering in the modulator loop, which shapes the quantization noise spectrum to move most of the noise energy to frequencies above 10 hz. the snr performance in the 0 hz to 10 hz range is conditioned to the 20-bit level in this fashion. the output of the comparator provides the digital input for the 1-bit dac, so the system functions as a negative feedback loop that minimizes the difference signal. the digital data that repre- sents the analog input voltage is in the duty cycle of the pulse train appearing at the output of the compara tor. it can be retrieved as a parallel binary data-word using a digital filter. - adcs are generally described by the order of the analog low-pass filter. a simple example of a first-order, - adc is shown in figure 8. this contains only a first-order, low-pass filter or integrator. it also illustrates the derivation of the alter- native name for these devices: charge-balancing adcs. the ad7703 uses a second-order, - modulator and a sophis- ticated digital filter that provides a rolling average of the sampled output. after power-up or if there is a step change in the input voltage, there is a settling time that must elapse before valid data is obtained.
rev. e ? ad7703 digital filtering the ad7703 s digital filter behaves like an analog filter, with a few minor differences. first, since digital filtering occurs after the analog-to-digital conversion, it can remove noise injected during the conversion process. analog filtering cannot do this. on the other hand, analog filtering can remove noise superim- posed on the analog signal before it reaches the adc. digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. to alleviate this problem, the ad7703 has overrange headroom built into the - modulator and digital filter that allows overrange excursions of 100 mv. if noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the gain in the input channel so that a full-scale input (2.5 v) gives only a half-scale input to the ad7703 (1.25 v). this will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by one bit (50%). filter characteristics the cutoff frequency of the digital filter is f clk /409600. at the maximum clock frequency of 4.096 mhz, the cutoff frequency of the filter is 10 hz and the data update rate is 4 khz. figure 9 shows the filter frequency response. this is a six-pole gaussian response that provides 55 db of 60 hz rejection for a 10 hz cutoff frequency. if the clock frequency is halved to give a 5 hz cutoff, 60 hz rejection is better than 90 db. 1 10 100 frequency ?hz 20 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 ?60 gain ?db f clk = 1mhz f clk = 2mhz f clk = 4mhz figure 9. frequency response of ad7703 filter since the ad7703 contains this low-pass filtering, there is a settling time associated with step function inputs, and data will be invalid after a step change until the settling time has elapsed. the ad7703 is, therefore, unsuitable for high speed multiplex- ing, where channels are switched and converted sequentially at high rates, as switching between channels can cause a step change in the input. however, slow multiplexing of the ad7703 is possible, provided that the settling time is allowed to elapse before data for the new channel is accessed. the output settling of the ad7703 in response to a step input change is shown in figure 10. the gaussian response has fast settling with no overshoot, and the worst-case settling time to 0.0007% is 125 ms with a 4.096 mhz master clock frequency. percent of final value 100 80 60 40 20 0 04080 120 160 time ?ms figure 10. ad7703 step response using the ad7703 system design considerations the ad7703 operates differently from successive approxima tion adcs or integrating adcs. since it samples the signal continu- ously, like a tracking adc, there is no need for a start convert command. the 20-bit output register is updated at a 4 khz rate, and the output can be read at any time, either synchronously or asynchronously. clocking the ad7703 requires a master clock input, which may be an exter- nal ttl/cmos compatible clock signal applied to the clkin pin (clkout not used). alternatively, a crystal of the correct frequency can be connected between clkin and clkout, when the clock circuit will function as a crystal controlled oscillator. figure 11 shows a simple model of the on-chip gate oscillator and table ii gives some typical capacitor values to be used with various resonators. ad7703 c2 * c1 * r1 5m x1 3 10pf 10pf g m = 1500 mho * see table ii 2 figure 11. on-chip gate oscillator
rev. e ad7703 ? table ii. resonator loading capacitors resonators c1 (pf) c2 (pf) ceramic 200 khz 330 470 455 khz 100 100 1.0 mhz 50 50 2.0 mhz 20 20 crystal 2.000 mhz 30 30 3.579 mhz 20 20 4.096 mhz none none the input sampling frequency, output data rate, filter character- istics, and calibration time are all directly related to the master clock frequency, f clkin , by the ratios given in the specification table under dynamic performance. therefore, the first step in system design with the ad7703 is to select a master clock fre- quency suitable for the bandwidth and output data rate required by the application. analog input ranges the ad7703 performs conversion relative to an externally supplied reference voltage that allows easy interfacing to ratio- metric systems. in addition, either unipolar or bipolar input voltage ranges may be selected using the bp/ up input. with bp/ up tied low, the input range is unipolar and the span is (v ref to v agnd ), where v agnd is the voltage at the device agnd pin. with bp/ up tied high, the input range is bipolar and the span is 2v ref . in the bipolar mode, both positive and negative full scale are directly determined by v ref . this offers superior tracking of positive and negative full scale and better midscale (bipolar zero) stability than bipolar schemes that simply scale and offset the input range. the digital output coding for the unipolar range is unipolar binary; for the bipolar range it is offset binary. bit weights for the uni polar and bipolar modes are shown in table i. accuracy s - d adcs, like vfcs and other integrating adcs, do not contain any source of nonmonotonicity and inherently offer no-missing-codes performance. the ad7703 achieves excellent linearity by the use of high quality, on-chip silicon dioxide capacitors, which have a very low capacitance/voltage coefficient. the device also achieves low input drift through the use of chopper-stabilized techniques in its input stage. to ensure excellent performance over time and temperature, the ad7703 uses digital calibration techniques that minimize offset and gain error to typically 4 lsb. autocalibration the ad7703 offers both self-calibration and system-calibration facilities. for calibration to occur, the on-chip microcontroller must record the modulator output for two different input condi- tions. these are the zero-scale and full-scale points. in unipolar self-calibration mode, the zero-scale point is v agnd and the full-scale point is v ref . with these readings, the microcontroller can calculate the gain slope for the input to output transfer function of the converter. in unipolar mode, the slope factor is determined by dividing the span between zero and full scale by 2 20 . in bipolar mode, it is determined by dividing the span by 2 19 since the inputs applied represent only half the total codes. in both unipolar and bipolar modes, the slope factor is saved and used to calculate the binary output code when an analog input is applied to the device. table iv gives the output code size after calibration. system calibration allows the ad7703 to compensate for system gain and offset errors. a typical circuit where this might be used is shown in figure 12. system calibration performs the same slope factor calculations as self-calibration but uses voltage values presented by the system to the a in pin for the zero- and full-scale points. there are two system calibration modes. the first mode offers system level calibration for system offset and system gain. this is a two step operation. the zero-scale point must be presented to the converter first. it must be ap plied to the converter before the calibration step is initiated and remain stable until the step is complete. the drdy output from the device will signal when the step is complete by going low. after the zero-scale point is calibrated, the full-scale point is applied and the second calibration step is initiated. again, the voltage must remain stable throughout the calibration step. the two step calibration mode offers another feature. after the sequence has been completed, additional offset calibrations can be performed by themselves to adjust the zero reference point to a new system zero reference value. this second system calibration mode uses an input voltage for the zero-scale calibration point but uses the v ref value for the full-scale point. system ref hi a in system ref lo analog mux a0 a1 signal conditioning ad7703 sclk sdata cal sc1 sc2 micro- computer a in figure 12. typical connections for system calibration
rev. e ?0 ad7703 initiating calibration table iii illustrates the calibration modes available in the ad 7703. not shown in the table is the function of the bp/ up pin, which determines whether the converter has been calibrated to mea- sure bipolar or unipolar signals. a calibration step is initiated by bringing the cal pin high for at least four clkin cycles and then bringing it low again. the states of sc1 and sc2 along with the bp/ up pin will determine the type of calibration to be performed. all three signals should be stable before the cal pin is taken positive. the sc1 and sc2 inputs are latched when cal goes high. the bp/ up input is not latched and, therefore, must remain in a fixed state throughout the calibration and measurement cycles. any time the state of the bp/ up is changed, a new calibration cycle must be performed to enable the ad 7703 to function properly in the new mode. when a calibration step is initiated, the drdy signal will go high and remain high until the step is finished. table iii shows the number of clock cycles each calibration requires. once a calibra- tion step is initiated, it must finish before a new calibration step can be executed. in the two step system calibration mode, the offset calibration step must be initiated before initiating the gain calibration step. when self-calibration is completed, drdy falls and the output port is updated with a data-word that represents the analog input signal. when a system calibration step is completed, drdy w ill fall and the output port will be updated with the appropriate data value (all 0s for the zero-scale point and all 1s for the full-scale point). in the system calibration mode, the digital filter must settle before the output code will represent the value of the analog input signal. tables iv and v indicate the output code size and output coding of the ad7703 in its various modes. in these tables, s off is the measured system offset in volts and s gain is the measured system gain at the full-scale point in volts. span and offset limits whenever a system calibration mode is used, there are limits on the amount of offset and span that can be accommodated. the range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 v ref and a maximum value of 2(v ref + 0.1 v). the amount of offset that can be accommodated depends on whether the unipolar or bipolar mode is being used. in unipolar mode, the system calibration modes can handle a maximum offset of 0.2 v ref and a minimum offset of C (v ref + 0.1 v). therefore the ad7703 in the unipolar mode can be calibrated to mimic bipolar operation. table iii. calibration truth table * calibration zero-scale full-scale calibration cal sc1 sc2 type calibration calibration sequence time 00 self-calibration v agnd v ref one step 3,145,655 clock cycles 11 system offset a in first step 1,052,599 clock cycles 01 system gain a in second step 1,068,813 clock cycles 10 system offset a in v ref one step 2,117,389 clock cycles * drdy remains high throughout the calibration sequence. in the self-calibration mode, drdy falls once the ad7703 has settled to the analog input. in all other modes, drdy falls as the device begins to settle. table iv. output code size after calibration 1 lsb calibration mode zero scale gain factor unipolar bipolar self-calibration v agnd v ref ( v ref C v agnd ) 1048576 2( v ref C v agnd ) 1048576 system calibration s off s gain ( s gain C s off ) 1048576 2( s gain C s off ) 1048576
rev. e ad7703 ?1 table v. output coding i nput voltage, unipolar mode i nput voltage, bipolar mode system calibration self-calibration output codes self-calibration system calibration >( s gain C 1.5 lsb) > (v ref C 1.5 lsb) fffff > (v ref C 1.5 lsb) > (s gain C 1.5 lsb) s gain C 1.5 lsb v ref C 1.5 lsb fffff ffffe v ref C 1.5 lsb s gain C 1.5 lsb (s gain C s off )/2 C 0.5 lsb (v ref C v agnd )/2 C 0.5 lsb 80000 7 ffff v agnd C 0.5 lsb s off C 0.5 lsb s off + 0.5 lsb v agnd + 0.5 lsb 00001 00000 C v ref + 0.5 lsb C s gain + 2 s off + 0.5 lsb < (s off + 0.5 lsb) < (v agnd + 0.5 lsb) 00000 < ( C v ref + 0.5 lsb) <( C s gain +2 s off + 0.5 lsb) in the bipolar mode, the system offset calibration range is re stricted to 0.4 v ref . it should be noted that the span restric- tions limit the amount of offset that can be calibrated. the span range of the converter in bipolar mode is equidistant around the voltage used for the zero-scale point. when the zero-scale point is calibrated, it must not cause either of the two endpoints of the bipolar transfer function to exceed the positive or the negative input overrange points (+v ref + 0.1) v or ( C v ref + 0.1) v. if the span range is set to a minimum (0.8 v ref ), the offset voltage can move +0.4 v ref without causing the endpoints of the trans- fer function to exceed the overrange points. alternatively, if the span range is set to 2v ref , the input offset cannot move more than +0.1 v or C 0.1 v before an endpoint of the transfer func- tion exceeds the input overrange limit. power-up and calibration a calibration cycle must be carried out after power-up to initial- ize the device to a consistent starting condition and correct calibration. the cal pin must be held high for at least four clock cycles, after which calibration is initiated on the falling edge of cal and takes a maximum of 3,145,655 clock cycles (approximately 768 ms with a 4.096 mhz clock). see table iii. the type of calibration cycle initiated by cal is determined by the sc1 and sc2 inputs, in accordance with table iii. drift considerations the ad7703 uses chopper stabilization techniques to minimize input offset drift. charge injection in the analog switches and leakage currents at the sampling node are the primary sources of offset voltage drift in the converter. figure 13 indicates the typical offset due to temperature changes after calibration at 25 c. drift is relatively flat up to 75 c. above this temperature, leakage current becomes the main source of offset drift. since leakage current doubles approximately every 10 c, the offset drifts accordingly. the value of the voltage on the sample capacitor is updated at a rate determined by the master clock; therefore, the amount of offset drift that occurs will be proportional to the elapsed time between samples. thus, to minimize offset drift at higher temperatures, higher clkin rates are recommended. gain drift within the converter depends mainly upon the tem- perature tracking of the internal capacitors. it is not affected by leakage currents so it is significantly less than offset drift. the typical gain drift of the ad7703 is less than 40 lsb over the specified temperature range. measurement errors due to offset drift or gain drift can be elimi nated at any time by recalibrating the converter. using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. integral and differential linearity are not significantly affected by temperature changes. bipolar offset ?lsbs 160 0 ?0 ?60 ?40 ?20 ?5 5 25 105 125 temperature ? c 80 ?5 ?5 45 65 85 clkin = 4.096mhz figure 13. typical bipolar offset vs. temperature after calibration at 25?
rev. e ?2 ad7703 input signal conditioning reference voltages from 1 v to 3 v may be used with the ad 7703, with little degradation in performance. input ranges that cannot be accommodated by this range of reference voltages may be achieved by input signal conditioning. this may take the form of gain to accommodate a smaller signal range, or passive attenua- tion to reduce a larger input voltage range. source resistance if passive attenuators are used in front of the ad7703, care must be taken to ensure that the source impedance is sufficiently low. the dc input resistance for the ad7703 is over 1 g w . in paral- lel with this, there is a small dynamic load that varies with the clock frequency (see figure 14). a in r1 r2 c ext a gnd ad7703 v os 100mv v in 1g c in 10pf figure 14. equivalent input circuit and input attenuator each time the analog input is sampled, a 10 pf capacitor draws a charge packet of maximum 1 pc (10 pf 100 mv) from the analog source with a frequency f clkin /256. for a 4.096 mhz clkin, this yields an average current draw of 16 na. after each sample, the ad7703 allows 62 clock periods for the input voltage to settle. the equation that defines settling time is v o = v in [1 C e C t / rc ] where v o , is the final settled value, v in , is the value of the input signal, r is the value of the input source resistance, and c is the 10 pf sample capacitor. the value of t is equal to 62/f clkin . the following equation can be developed, which gives the maxi- mum allowable source resistance, r s(max) , for an error of v e : r fpfmvv s max clkin e () ()( /) = 62 10 100 ln provided the source resistance is less than this value, the analog input will settle within the desired error band in the requisite 62 clock periods. insufficient settling leads to offset errors. these can be calibrated in system calibration schemes. if a limit of 600 nv (0.25 lsb at 20 bits) is set for the maximum offset voltage, then the maximum allowable source resistance is 125 k w from the above equation, assuming that there is no external stray capacitance. an rc filter may be added in front of the ad7703 to reduce high frequency noise. with an external capacitor added from a in to agnd, the following equation will specify the maximum allowable source resistance: r fcc mv c cc v s max clkin in ext in in ext e () () () = + + ? ? ? ? ? ? ? 62 100 ln the practical limit to the maximum value of source resistance is thermal (johnson) noise. a practical resistor may be modeled as an ideal (noiseless) resistor in series with a noise voltage source or in parallel with a noise current source: v ktrf volts n = 4 ik tf r amperes n = 4/ where k is boltzmann s constant (1.38 10 C 23 j/k), and t is temperature in degrees kelvin ( c + 273). active signal conditioning circuits such as op amps generally do not suffer from problems of high source impedance. their open- loop output resistance is normally only tens of ohms and, in any case, most modern general-purpose op amps have sufficiently fast closed-loop settling time for this not to be a problem. offset volt- age in op amps can be eliminated in a system calibration routine. antialias considerations the digital filter of the ad7703 does not provide any rejection at integer multiples of the sampling frequency (nf clkin /256, where n = 1, 2, 3 . . . ). with a 4.096 mhz master clock, there are narrow (10 hz) bands at 16 khz, 32 khz, 48 khz, and so on, where noise passes unattenuated to the output. however, due to the ad7703 s high oversampling ratio of 800 (16 khz to 20 hz), these bands occupy only a small fraction of the spectrum, and most broadband noise is filtered. the reduction in broadband noise is given by ee ff e out in c s in == 20 035 /. where e in and e out are rms noise terms referred to the input, f c is the filter C 3 db corner frequency (f clkin /409600), and f s is the sampling frequency (f clkin /256). since the ratio of f s to f clkin is fixed, the digital filter reduces broadband white noise by 96.5% independent of the master clock frequency.
rev. e ad7703 ?3 voltage reference connections the voltage applied to the v ref pin defines the analog input range. the specified reference voltage is 2.5 v, but the ad7703 will operate with reference voltages from 1 v to 3 v with little degradation in performance. the reference input presents exactly the same dynamic load as the analog input, but in the case of the reference input, source resistance and long settling time introduce gain errors rather than offset errors. fortunately, most precision references have sufficiently low output impedance and wide enough bandwidth to settle to the required accuracy within 62 clock cycles. the digital filter of the ad7703 removes noise from the refer ence input, just as it does with noise at the analog input, and the same limitations apply regarding lack of noise rejection at integer multiples of the sampling frequency. note that the reference should be chosen to minimize noise below 10 hz. the ad7703 typically exhibits 1.6 lsb rms noise in its measurements. this specification assumes a clean reference. many monolithic band gap references are available, which can supply the 2.5 v needed for the ad7703. however, some of these are not specified for noise, especially in the 0.1 hz to 10 hz bandwidth. if the reference noise in this bandwidth is excessive, it can degrade the performance of the ad7703. recommended references are the ad580 and the lt1019. both of these 2.5 v references typically have less than 10 v p-p noise in the 0.1 hz to 10 hz band. power supplies and grounding agnd is the ground reference voltage for the ad7703, and is completely independent of dgnd. any noise riding on the agnd input with respect to the system analog ground will cause con- version errors. agnd should, therefore, be used as the system ground and also as the ground for the analog input and the reference voltage. the analog and digital power supplies to the ad7703 are inde- pendent and separately pinned out to minimize coupling between analog and digital sections of the device. the digital filter will provide rejection of broadband noise on the power supplies, except at integer multiples of the sampling frequency. there- fore, the two analog supplies should be individually decoupled to agnd using 100 nf ceramic capacitors to provide power supply noise rejection at these frequencies. the two digital supplies should similarly be decoupled to dgnd. the positive digital supply (dv dd ) must never exceed the positive analog supply (av dd ) by more than 0.3 v. power supply sequenc- ing is, therefore, important. if separate analog and digital supplies are used, care must be taken to ensure that the analog supply is powered up first. it is also important that power is applied to the ad7703 before signals at v ref , a in , or the logic input pins in order to avoid any possibility of latch-up. if separate supplies are used for the ad7703 and the system digital circuitry, the ad7703 should be powered up first. a typical scheme for powering the ad7703 from a single set of 5 v rails is shown in figure 7. in this circuit, av dd and dv dd are brought along separate tracks from the same 5 v supply. thus, there is no possibility of the digital supply coming up before the analog supply. sleep mode the low power standby mode is initiated by taking the sleep input low, which shuts down all analog and digital circuits and reduces power consumption to 10 w. when coming out of sleep mode, it is sometimes possible (when using a crystal to generate clkin, for example) to lose the calibration coeffi- cients. therefore, it is advisable as a safeguard to always do a calibration cycle after coming out of sleep mode. digital interface the ad7703 s serial communications port allows easy inter- facing to industry-standard microprocessors. two different modes of operation are available, optimized for different types of interface.
rev. e ?4 ad7703 synchronous self-clocking mode (ssc) the ssc mode (mode pin high) allows easy interfacing to serial-parallel conversion circuits in systems with parallel data communication. this mode allows interfacing to 74xx299 universal shift registers without any additional decoding. the ssc mode can also be used with microprocessors such as the 68hc11 and 68hc05, which allow an external device to clock their serial port. figure 15 shows the timing diagram for the ssc mode. data is clocked out by an internally generated serial clock. the ad 7703 divides each sampling interval into 16 distinct periods. eight periods of 64 clock pulses are for analog settling and eight peri- ods of 64 clock pulses are for digital computation. the status of cs is polled at the beginning of each digital computation pe riod. if it is low at any of these times, then sclk will become active and the data-word currently in the output register will be trans- mitted, msb first. after the lsb has been transmitted, drdy will go high until the new data-word becomes available. if cs , having been brought low, is taken high again at any time during data transmission, sdata and sclk will go three-state after the current bit finishes. if cs is subsequently brought low, transmission will resume with the next bit during the subse- quent digital computation period. if transmission has not been initiated and completed by the time the next data-word is avail- able, drdy will go high for four clock cycles then low again as the new word is loaded into the output register. a more detailed diagram of the data transmission in the ssc mode is shown in figure 16. data bits change on the falling edge of sclk and are valid on the rising edge of sclk. analog time 0 digital time 7 sclk (o) sdata (o) hi-z hi-z hi-z hi-z msb drdy (o) digital time 0 cs polled cs (i) internal status 72 clkin cycles 64 clkin cycles 64 clkin cycles 1024 clkin cycles lsb figure 15. timing diagram for ssc transmission mode clkin (i) drdy (o) sdata (o) db19 (msb) db18 db2 db1 db0 (lsb) hi-z hi-z sclk (o) hi-z hi-z cs (i) 72 clkin cycles db17 figure 16. ssc mode showing data timing relative to sclk
rev. e ad7703 ?5 synchronous external clock mode (sec) the sec mode (mode pin grounded) is designed for direct interface to the synchronous serial ports of industry-standard microprocessors such as the 68hc11 and 68hc05. the sec mode also allows customized interfaces, using i/o port pins, to microprocessors that do not have a direct fit with the ad7703 s other mode. as shown in figure 17, a falling edge on cs enables the serial data output with the msb initially valid. subsequent data bits change on the falling edge of an externally supplied sclk. a fter the lsb has been transmitted, drdy and sdata go three-state. if cs is low and the ad7703 is still transmitting data when a new data-word becomes available, the old data-word continues to be transmitted and the new data is lost. if cs is taken high at any time during data transmission, s data will go three-state immediately. if cs returns low, the ad7703 will continue transmission with the same data bit. if transmis- sion has not been initiated and completed by the time the next data-word becomes available, and if cs is high, drdy returns high for four clock cycles, then falls as the new word is loaded into the output register. digital noise and output loading as mentioned earlier, the ad7703 divides its internal timing into two distinct phases, analog sampling and settling and digi- tal computation. in the ssc mode, data is transmitted only during the digital computation periods, to minimize the effects of digital noise on analog performance. in the sec mode, data transmission is externally controlled, so this automatic safeguard does not exist. to compensate, synchronize the ad7703 to the digital system clock via clkin when used in the sec mode. whatever mode of operation is used, resistive and capacitive loads on digital outputs should be minimized in order to reduce crosstalk between analog and digital portions of the circuit. for this reason, connection to low power cmos logic such as one of the 4000 series or 74c families is recommended. drdy (o) sdata (o) db19 (msb) db18 db2 db1 db0 (lsb) hi-z sclk (o) hi-z cs (i) db17 figure 17. timing diagram for sec mode
rev. e c01165??/03(e) ?6 ad7703 outline dimensions revision history location page 4/03?ata sheet changed from rev. d to rev. e. updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 20-lead plastic dual in-line package [pdip] (n-20) dimensions shown in inches and (millimeters) 20 1 10 11 0.985 (25.02) 0.965 (24.51) 0.945 (24.00) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) bsc 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095-ae 20-lead ceramic dual in-line package [cerdip] (q-20) dimensions shown in inches and (millimeters) 20 110 11 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 1.060 (26.92) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 20-lead standard small outline package [soic] wide body (r-20) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ac 0.75 (0.0295) 0.25 (0.0098) 20 11 10 1 0.32 (0.0126) 0.23 (0.0091) 8 0 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 13.00 (0.5118) 12.60 (0.4961) coplanarity 0.10

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